In this video I walk through one of the easiest ways to accidentally kneecap a new PC build: misunderstanding PCIe “data lanes.” When you start stacking adapters—10Gb NICs, SAS HBAs, M.2 add-in cards, capture cards—everything looks like it should “just work” because the slots physically fit. But PCIe is really about how many bi-directional lanes the CPU and chipset can actually provide, and how the motherboard routes and shares them. I break down the difference between CPU lanes and chipset lanes, and why the chipset is basically a traffic manager that can introduce sharing and bottlenecks depending on the board design. Then I show how to think about lane requirements per adapter (x1/x4/x8/x16), how lanes get negotiated in motherboard logic, and why some slots drop to fewer lanes when you populate other slots or M.2 devices. I use real examples with boards like the ASUS Prime Z370-P and ASUS Prime X570 to illustrate how lane layouts differ by platform, and I close with the kinds of lane-shift anomalies that can make a “perfectly reasonable” parts list behave strangely. The takeaway: read the manual lane tables, plan your slot population, and match your CPU/platform to the expansion you actually need.