In this video, I sat with Sahej (DTU alumnus) who is currently working at Renesas as an Associate Engineer in the Performance Verification team. We went step-by-step through his on-campus journey—DTU admission via JEE Mains + JAC counselling, why he chose Electrical at DTU, and how the college ecosystem, labs, and supportive professors helped him explore VLSI seriously. He also shared a very practical view on B.Tech vs M.Tech: if your campus has strong VLSI opportunities, try placements first and keep M.Tech as a backup plan. Then we got into the exact Renesas on-campus selection process: an MCQ test (50–70 questions in ~1 hour), CGPA filtering (he recommends targeting 8.5+ to stay safe), and then three technical rounds plus one behavioral/aptitude round. The interview focus was clear—digital fundamentals (combinational/sequential logic, FSM, counters, FIFO), basics of STA, VLSI flow, and finally writing Verilog/SystemVerilog testbenches. We also discussed what “performance verification” actually means versus performance modeling and design verification, and the key metrics you validate on RTL—latency and bandwidth (and sometimes FPS depending on the IP). His advice for freshers is simple: failing to plan is planning to fail—start early, practice Verilog on platforms like EDA Playground, and be honest about what you know while showing you’re ready to learn and hustle.